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LTC4557 Dual SIM/Smart Card Power Supply and Interface
FEATURES
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DESCRIPTIO
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Power Management and Signal Level Translators for Two SIM Cards or Smart Cards Independent 1.8V/3V VCC Control for Both Cards Automatic Level Translation ISO7816, ETSI and EMV Compatible Dynamic Pull-Ups Deliver Fast Signal Rise Times* Built-In Fault Protection Circuitry Automatic Activation/Deactivation Sequencing Circuitry Low Operating/Shutdown Current >10kV ESD on SIM Card Pins Compatible with EMV Fault Tolerance Requirements Available in 16-Lead (3mm x 3mm) QFN Package
The LTC(R)4557 provides power conversion and signal level translation needed for 2.5G and 3G cellular telephones to interface with 1.8V or 3V subscriber identity modules (SIMs). The part meets all requirements for 1.8V and 3V SIMs. The part contains LDO regulators to power 1.8V or 3V SIM cards from a 2.7V to 5.5V input. The output voltages can be set using the two voltage selection pins and up to 50mA of load current can be supplied. Internal level translators allow controllers operating with supplies as low as 1.2V to interface with 1.8V or 3V smart cards. Battery life is maximized by a low operating current of less than 100A and a shutdown current of less than 1A. Board area is minimized by the low profile 3mm x 3mm x 0.75mm leadless QFN package.
, LTC and LT are registered trademarks of Linear Technology Corporation. *U.S. Patent No. 6,356,140
APPLICATIO S
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GSM and 3G Cellular Phones Wireless P.O.S. Terminals Multiple SAM Card Interface
TYPICAL APPLICATIO
DVCC 0.1F DVCC CLKIN RSTIN DATA CONTROLLER
VBATT DVCC 1.2V TO 4.4V 3V TO 6V 0.1F VBATT I/OA RSTA CLKA VCCA LTC4557 GND 1F VCCB ENABLE M0 M1 CLKB RSTB I/OB C1 C3 C2 C7 VCC CLK 1.8V/3V SMART RST CARD I/O GND C5
4557 TA01
C7 C2 C3 C1 1F
I/O RST 1.8V/3V SIM CLK CARD VCC GND C5
RSTX 5V/DIV CLKX 5V/DIV I/OX 5V/DIV VCCX 2V/DIV CVCCX = 1F 10s/DIV
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Deactivation Sequence
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LTC4557
ABSOLUTE
(Note 1)
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RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
CLKA
RSTA
I/OA
DATA
VBATT, DVCC, DATA, RSTIN, CLKIN, ENABLE, M0, M1 to GND ............................ - 0.3V to 6V I/OA, CLKA, RSTA ........................ - 0.3V to VCCA + 0.3V I/OB, CLKB, RSTB ........................ - 0.3V to VCCB + 0.3V ICCA,B (Note 4) ...................................................... 80mA VCCA,B Short-Circuit Duration ......................... Indefinite Operating Temperature Range (Note 3) .. - 40C to 85C Storage Temperature Range ................... - 65C to 125
ENABLE
RSTB
CLKB
I/OB
ORDER PART NUMBER LTC4557EUD
12 M0 11 M1 10 CLKIN 9 RSTIN
16 15 14 13 VCCB 1 DVCC 2 VBATT 3 VCCA 4 5 6 7 8 17
UD PART MARKING LAHP
UD PACKAGE 16-LEAD (3mm x 3mm) PLASTIC QFN TJMAX = 125C, JA = 68C/W, JC = 42C/W EXPOSED PAD (PIN 17) IS GND (MUST BE SOLDERED TO PCB)
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER VBATT Operating Voltage IVBATT Operating Current DVCC Operating Voltage IDVCC Operating Current IDVCC Shutdown Current IVBATT Shutdown Current Input Power Supply
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VBATT = 3.3V, DVCC = 1.8V, unless otherwise specified.
CONDITIONS
q
MIN 2.7
TYP
MAX 5.5
UNITS V A A V A A A A V V ms V V
VCCA = 3V, VCCB = 0V, ICCA = ICCB = 0A VCCA = 1.8V, VCCB = 0V, ICCA = ICCB = 0A
q q q q q
65 65 1.2 6 0.1 0.4 0.1 2.75 1.65 3.0 1.8 1.3
100 100 5.5 10 1 2.5 1.0 3.25 1.95 2.5 0.2
DVCC = 0V SIM Card Supplies VCCA,B Output Voltage Channel Turn-On Time CLKA, CLKB VOL VOH Low Level Output Voltage High Level Output Voltage Rise, Fall Time CLKA, CLKB Frequency RSTA, RSTB VOL VOH Low Level Output Voltage High Level Output Voltage Rise, Fall Time Sink Current = -200A (Note 2) Source Current = 200A (Note 2) Loaded with 33pF (10% to 90%) (Note 2) Sink Current = -200A (Note 2) Source Current = 200A (Note 2) Loaded with 33pF (10% to 90%) (Note 2) (Note 2) 3V Mode, 0mA < ICCA,B < 50mA 1.8V Mode, 0mA < ICCA,B < 3OmA ICCA,B = 0mA, ENABLE to IOA/B
q q
q q q
q q VCCA,B -
0.2
q q
16 10 0.2 0.2
q q VCCA,B - q
100
2
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ns MHz V V ns
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LTC4557
ELECTRICAL CHARACTERISTICS
SYMBOL I/OA, I/OB VOL VOH Low Level Output Voltage High Level Output Voltage Rise Time Short-Circuit Current DATA VOL VOH Low Level Output Voltage High Level Output Voltage Rise Time RSTIN, CLKIN, ENABLE, M0, M1 VIL VIH Low Input Threshold High Input Threshold Input Current (IIH, IIL) PARAMETER
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VBATT = 3.3V, DVCC = 1.8V, unless otherwise specified.
CONDITIONS Sink Current = -1mA (VDATA = 0V) (Note 2) Source Current = 20A (VDATA = VDVCC) (Note 2) Loaded with 33pF (10% to 90%) (Note 2) VDATA = 0V (Note 2) Sink Current = -500A (VI/OA,B = 0V) Source Current = 20A (VI/OA,B = VCCA,B) Loaded with 33pF (10% to 90%)
q q q q
MIN
TYP
MAX 0.3
UNITS V V
0.85 * VCCA,B 200 5 500 10 0.3 0.8 * DVCC 200 500 0.15 * DVCC 0.85 * DVCC -1 1
ns mA V V ns V V A
q q q
q q q
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: This specification applies to both 1.8V and 3V smart cards.
Note 3: The LTC4557E is guaranteed to meet performance specifications from 0C to 70C. Specifications over the - 40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 4: Based on long term current density limitations.
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LTC4557 TYPICAL PERFOR A CE CHARACTERISTICS
No Load Supply Current vs VBATT
80 TA = 25C ICCA = ICCB = 0A 6.0
75
SHORT-CIRCUIT CURRENT (mA)
SUPPLY CURRENT (A)
SUPPLY CURRENT (A)
DROPOUT 70 VCCX = 3V 65 VCCX = 1.8V 60
55 2.7 3.1 3.5 3.9 4.3 4.7 SUPPLY VOLTAGE (V) 5.1 5.5
VBATT Shutdown Current vs Supply Voltage
3.0 2.5
SUPPLY CURRENT (A)
SUPPLY CURRENT (A)
VDVCC = 1.8V
2.0 1.5 1.0
0.5 0 2.7
3.1
4.7 3.5 3.9 4.3 SUPPLY VOLTAGE (V)
Data - I/O Channel, CL = 40pF
I/0X 1V/DIV RSTX 5V/DIV CLKX 5V/DIV DATA 1V/DIV I/OX 5V/DIV VCCX 2V/DIV CL = 40pF 200ns/DIV
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I/O X Short-Circuit Current vs Temperature
140
VDVCC = VBATT = 5.5V VCCX = 3V
VBATT Quiescent Current (IVBATT - ICC) vs Load Current
120 100 80 60 40 20 TA = 25C VBATT = 3.1V
5.5
5.0
4.5
4.0 -40
0
-15 35 10 TEMPERATURE (C) 60 85
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100 1000 10000 LOAD CURRENT (A)
100000
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DVCC Shutdown Current vs Supply Voltage
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6 SUPPLY VOLTAGE (V)
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VBATT = 5.5V TA = -40C TO 85C
TA = -40C TA = 25C
TA = 85C
5.1
5.5
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Deactivation Sequence, CVCCX = 1F
CVCCX = 1F
10s/DIV
4557 G07
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LTC4557
PI FU CTIO S
DVCC (Pin 2): Power. Reference voltage for the control logic. VBATT (Pin 3): Power. Supply voltage for the analog sections of the LTC4557. VCCA/VCCB (Pins 4, 1): Card Socket. The VCCA/VCCB pins should be connected to the VCC pins of the respective card sockets. The activation of the VCCA/VCCB pins is controlled by the M0, M1 and ENABLE inputs. They can be set to 0V, 1.8V or 3V. Only one of the two, either VCCA or VCCB, may be active at a time. CLKA/CLKB (Pins 5, 16): Card Socket. The CLKA/CLKB pins should be connected to the CLK pins of the respective card sockets. The CLKA/CLKB signals are derived from the CLKIN pin. They provide a level shifted CLKIN signal to the selected card. The CLKA/CLKB pins are gated off until VCCA/VCCB attain their correct values. RSTA/RSTB (Pins 6, 15): Card Socket. The RSTA/RSTB pins should be connected to the RST pins of the respective card sockets. The RSTA/RSTB signals are derived from the RSTIN pin. When a card is selected, its RST pin follows RSTIN. The RSTA/RSTB pins are gated off until VCCA/VCCB attain their correct values. I/OA, I/OB (Pins 7, 14): Card Socket. The I/OA, I/OB pins connect to the I/O pins of the respective card sockets. When a card is selected, its I/O pin transmits/receives data to/from the DATA pin. The I/OA, I/OB pins are gated off until VCCA/VCCB attain their correct values. DATA (Pin 8): Input/Output. Microcontroller side data I/O pin. The DATA pin provides the bidirectional communication path to both cards. Only one of the cards may be selected to communicate via the DATA pin. The pin possesses a dynamically activated pull-up current source, allowing the controller to use an open-drain output. The current source maintains a HIGH state. This pin is held HIGH by a weak pull-up when the ENABLE pin is LOW. RSTIN (Pin 9): Input. The RSTIN pin supplies the reset signal to the cards. It is level shifted and transmitted directly to the RST pin of the selected card. CLKIN (Pin 10): Input. The CLKIN pin supplies the clock signal to the cards. It is level shifted and transmitted directly to the CLK pin of the selected card. M0/M1 (Pins 12, 11): Inputs. The M0 and M1 pins select which set of SIM/smart card pins are active and at which voltage level they operate. The truth table for these pins follows:
M1 0 0 1 1 M0 0 1 0 1 SELECTED CARD/VOLTAGE Card A/1.8V Card A/3V Card B/1.8V Card B/3V
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ENABLE (Pin 13): Input. The ENABLE pin shuts down the chip when LOW. EXPOSED PAD (Pin 17): Chip Ground. This ground pad must be soldered directly to a PCB ground plane.
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LTC4557
BLOCK DIAGRA
VCCA 4
I/OA 7
RSTA 6
CLKA 5
DATA 8 RSTIN 9 CLKIN 10 17 GND 13 CONTROL LOGIC
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DVCC 2 VBATT 3 LDOA LDOB 1 VCCB DVCC 14 I/OB 15 RSTB 16 CLKB DVCC 12 11 M1
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ENABLE M0
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LTC4557
OPERATIO
The LTC4557 features two independent smart card channels. Only one of these channels may operate at a time. Each channel is able to output two voltage levels: 1.8V and 3V. The channel selection and voltage selection are controlled by the ENABLE, M0 and M1 pins as shown in Table 1.
Table 1. Channel and Voltage Truth Table
ENABLE 1 1 1 1 0 M1 0 0 1 1 X M0 0 1 0 1 X SELECTED CARD/VOLTAGE Card A/1.8V Card A/3V Card B/1.8V Card B/3V A and B Disabled
Bidirectional Channels The bidirectional channels are level shifted to the appropriate VCCA,B voltages at the I/OA,B pins. An NMOS pass transistor performs the level shifting. The gate of the NMOS transistor is biased such that the transistor is completely off when both sides have relinquished the channel. If one side of the channel asserts a LOW, then the transistor will convey the LOW to the other side. Note that current passes from the receiving side of the channel to the transmitting side. The low output voltage of the receiving side will be dependent upon the voltage at the transmitting side plus the IR drop of the pass transistor.
LOCAL SUPPLY ISTART
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When a card socket is selected, it becomes a candidate to drive data on the DATA pin and likewise receive data from the DATA pin. When a card socket is deselected, the voltage on its I/OA,B pin will be disabled and set to LOW. If both cards are deselected, a weak pull-up ensures that the DATA pin is held HIGH. Dynamic Pull-up Current Sources The current sources on the bidirectional pins (DATA/ I/OA,B) are dynamically activated to achieve a fast rise time with a relatively small static current. Once a bidirectional pin is relinquished, a small start-up current begins to charge the node. An edge rate detector determines if the pin is released by comparing its slew rate with an internal reference value. If a valid transition is detected, a large pull-up current enhances the edge rate on the node. The higher slew rate corroborates the decision to charge the node thereby affecting a dynamic form of hysteresis. Reset Channels When a card is selected, the reset channel provides a level shifted path from the RSTIN pin to the RSTA,B pin. When a card is deselected its reset pin is pulled LOW.
+ -
dv dt BIDIRECTIONAL PIN
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VREF
Figure 1. Dynamic Pull-Up Current Source
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LTC4557
OPERATIO
Activation/Deactivation Activation and deactivation sequencing is handled by built-in circuitry. The activation sequence is initiated by bringing the ENABLE pin HIGH. The activation sequence is outlined below: 1. The RST, CLK and I/O pins are held LOW. 2. VCC is enabled. 3. After VCC is stable at its selected level, The I/O and RST channels are enabled. 4. The clock channel is enabled on the rising edge of the second clock cycle after the I/O pin is enabled. The deactivation sequence is initiated by bringing the ENABLE pin LOW. The deactivation sequence is outlined below: 1. The reset channel is disabled and RST is brought LOW. 2. The clock channel is disabled and the CLK pin is brought LOW two clock cycles after ENABLE is brought LOW. If the clock is not running, the clock channel will be disabled approximately 9s after the ENABLE pin is brought LOW.
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3. The I/O channel is disabled and the I/O pin is brought LOW approximately 9s after the ENABLE is brought LOW. 4. VCC will be depowered after the I/O pin is brought LOW. The activation or deactivation sequences will take place every time a card socket is enabled or disabled. Fault Protection The VCC, I/O, RST and CLK pins are all protected against short-circuit faults. While there are no logic outputs to indicate that a fault has occurred, these pins will be able to tolerate the fault condition until it has been removed. The VCCA,B, I/OA,B, and RSTA,B pins possess fault protection circuitry which will limit the current available to the pins. Each VCC pin is capable of supplying approximately 90mA (typ) before the output voltage is reduced. The CLKA,B pins are designed to tolerate faults by reducing the current drive capability of their output stages. After a fault is detected by the internal fault detection logic, the logic waits for a fault detection delay to elapse before reducing the current drive capability of the output stage.
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LTC4557
APPLICATIO S I FOR ATIO
10kV ESD Protection All smart card pins (CLKA,B, RSTA,B, I/OA,B, VCCA,B and GND) can withstand over 10kV of human body model ESD in-situ. In order to ensure proper ESD protection, careful board layout is required. The GND pad should be tied directly to a ground plane. The VCCA,B capacitors should be located very close to the VCCA,B pins and tied immediately to the ground plane. Capacitor Selection A total of four capacitors are required for proper bypassing of the LTC4557. An input bypass capacitor is required at VBATT and DVCC. Output bypass capacitors are required on each of the smart card VCCA,B pins. Due to their extremely low equivalent series resistance (ESR), only multilayer ceramic chip capacitors should be used to ensure proper stability and ESD protection. There are several types of ceramic capacitors available each having considerably different characteristics. For example, X7R/X5R ceramic capacitors have excellent voltage and temperature stability but relatively low packing density. Y5V ceramic capacitors have apparently higher packing density but poor performance over their rated voltage or temperature ranges. Under certain voltage and temperature conditions Y5V and X7R/X5R ceramic
CVCC, VCCA/B CDVCC, DVCC
VCCX CLKX LTC4557 RSTX I/OX 20pF 100 100 100 20pF 20pF 0.1F
Figure 2. Additional Components for Improved Compliance Testing
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capacitors can be compared directly by case size rather than specified value for a desired minimum capacitance. The VCCA,B outputs should be bypassed to GND with a 1F capacitor. VBATT should be bypassed with a 0.1F ceramic capacitor. Capacitors should be placed as close to the LTC4557 as possible for improved ESD tolerance. The following capacitors are recommended for use with the LTC4557:
TYPE X5R X5R VALUE 1F 0.1F CASE SIZE MURATA PART NUMBER 0603 0402 GRM188R60J105KA01 GRM155R61A104KA01
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Compliance Testing Inductance due to long leads on type approval equipment can cause ringing and overshoot that leads to testing problems. Small amounts of capacitance and damping resistors can be included in the application without compromising the normal electrical performance of the LTC4557 or smart card system. Generally a 100 resistor and a 20pF capacitor will accomplish this as shown in Figure 2.
1F C1 C3 SMART CARD C2 SOCKET C7 C5
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LTC4557
APPLICATIO S I FOR ATIO
Shutdown Modes
The LTC4557 can enter a low current shutdown mode by one of two methods. First, the ENABLE pin can be brought LOW by the controller to directly shut down the part. The other way is to lower DVCC below 1.2V, at which point the power-on-reset circuit automatically puts the part into shutdown mode.
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Ultralow Shutdown Current In either of the two shutdown modes, the shutdown current is less than 1A. For applications that require virtually zero shutdown current, the DVCC pin can be grounded. This will reduce the VBATT current to well under a single microampere.
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LTC4557
PACKAGE DESCRIPTIO
3.50 0.05 1.45 0.05 2.10 0.05 (4 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.75 0.05
PIN 1 TOP MARK (NOTE 6) 1.45 0.10 (4-SIDES)
0.00 - 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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UD Package 16-Lead Plastic QFN (3mm x 3mm)
(Reference LTC DWG # 05-08-1691)
0.70 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD 0.23 TYP R = 0.115 (4 SIDES) TYP 15 16 0.40 0.10 1 2 3.00 0.10 (4 SIDES)
(UD) QFN 0603
0.200 REF
0.25 0.05 0.50 BSC
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LTC4557
TYPICAL APPLICATIO
CONTROLLER
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
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VBATT DVCC 1.2V TO 4.4V 3V TO 6V DVCC C3 2 0.1F DVCC 10 CLKIN 9 RSTIN 8 DATA 3 VBATT 5 CLKA 6 RSTA 7 I/OA 4 VCCA GND VCCB ENABLE M0 M1 CLKB RSTB I/OB 17 1 16 15 14 C1 1F C2 1F C4 0.1F C7 C2 C3 C1 CLK RST 1.8V/3V SIM I/O CARD VCC GND C5 C1 C3 C2 C7 LTC4557 13 12 11 VCC CLK 1.8V/3V SMART RST CARD I/O GND C5
4557 TA02
4557f LT/TP 0204 1K * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2004

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